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Kushan M.

Analog Design & Operations Engineer

Guwahati, India

Global rank:

18,891 / 142,502

Skill pts: 5

AMD Xilinx SDK Cadence Design Entry HDL Cadence PSpice Cadence Virtuoso Prototyping

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About

I am an Electronics & Communication Engineer specializing in Analog IC Design, VLSI, mixed-signal circuits, semiconductor engineering, and hardware development, with additional experience in technical research, project execution, and engineering documentation.

My primary expertise is transistor-level analog circuit design and simulation using Cadence Virtuoso and CMOS technologies. I have worked with differential amplifiers, current mirrors, common-source amplifiers, cascode and folded-cascode architectures, biasing circuits, current sources, CMOS operational amplifiers, two-stage op-amps, and DAC-integrated analog systems. I am comfortable with transistor sizing, bias analysis, circuit optimization, and simulation-driven design.

I have experience evaluating gain, bandwidth, GBW, phase margin, gain margin, slew rate, ICMR, CMRR, PSRR, noise, power consumption, stability, DC operating point, transient response, and PVT/corner performance. I can assist with circuit debugging, performance analysis, architecture comparison, and optimization.

My VLSI and mixed-signal interests also include PLLs, Phase Frequency Detectors (PFDs), VCOs, frequency-synthesis concepts, feedback systems, and high-speed semiconductor architectures. I have worked on research-oriented exploration of PFD architectures and technical circuit concepts, with interest in research-paper development and patent-oriented innovation.

I also have exposure to CMOS layout and physical-design concepts, including device matching, parasitic considerations, layout optimization, and implementation-oriented design. In hardware engineering, I can contribute to PCB design, electronic circuit development, component selection, prototyping, debugging, and system-level hardware projects.

My broader technical background includes digital electronics, CMOS logic, RTL concepts, FPGA architecture, semiconductor design methodologies, RTL-to-GDSII flow concepts, basic C and Python, Linux, data analysis, and technical documentation.

I can contribute to projects involving Analog IC Design, CMOS Circuit Design, VLSI, Mixed-Signal Design, Cadence Virtuoso, Circuit Simulation, PLL, PFD, VCO, CMOS Layout, PCB Design, Hardware Engineering, Semiconductor Research, Technical Research, and Engineering Documentation.

I approach every project systematically: understand specifications, select an appropriate architecture, implement the design, simulate and validate performance, identify limitations, and optimize the final solution. My additional experience in project coordination, stakeholder communication, documentation, and startup operations enables me to contribute effectively to multidisciplinary engineering projects.

I am particularly interested in challenging projects involving analog and mixed-signal ICs, VLSI, semiconductor innovation, PLL/PFD/VCO architectures, PCB and hardware development, research, and circuit design.

Experience

Founder & Research Lead RenewVolt · Self-employed Jun 2024 – Present 2 yrs 2 mos AS, India Led embedded power-electronics hardware for voltage stabilization and energy efficiency, integrating sensing, control and IoT
monitoring; managed documentation, prototype validation and multidisciplinary engineering.
FPGA Design Engineer SION Semiconductors · Full-time Feb 2026 – Aug 2026 6 mos Bengaluru, KA, India Developed Verilog RTL for AXI/APB/SPI; ran Vivado synthesis, implementation and timing analysis; fixed setup/hold paths
through constraints and logic restructuring. Performed multi-clock CDC analysis/synchronizer fixes and built UVM environments
with constrained-random stimulus, SVA, coverage and regressions
Mixed Signal Design Engineer Lab and Lectures Pvt. Ltd · Part-time May 2026 – Jul 2026 2 mos Bengaluru, KA, India Designed a split-CDAC asynchronous SAR ADC with bootstrapped switches, capacitor array and SAR logic. Characterized power,
settling, linearity, matching and latency through DC/AC/transient/corner simulations; defined analog-digital timing constraints
and collaborated on IP integration.
Training and Placement Coordinator Assam University · Part-time May 2025 – May 2026 1 yrs Silchar, AS, India Serve as a primary liaison among recruiters, university administration, faculty, and students throughout campus recruitment
campaigns.
• Conducted recruiter outreach and placement follow-ups with MGH Infrastructure, Amaron, Air India, Star Cement, C-Zentrix,
Abbott Pharmaceuticals, Finncle, ORC Engineering, Autoline Industries, Fractal Analytics, Mahindra, Kotak Mahindra Bank,
ICICI, and other employers.
• Helped secure campus placements for 24 students, including 19 from Electronics and Communication Engineering and five
from other departments.
• Coordinate hiring drives, interviews, pre-placement talks, documentation, candidate updates, scheduling issues, and postplacement
communication across multiple industries.
• Prepare official notices, presentation materials, trackers, and communication workflows that improve information flow and
execution.
Operations & Workflow Coordinator Intervue.io · Full-time Sep 2025 – Feb 2026 5 mos Bengaluru, KA, India Managed an end-to-end relationship pipeline of more than 1,300 technology professionals across software engineering, cloud,
DevOps, data, AI/ML, mobile, and system-design domains.
• Converted 70+ qualified professionals into active platform users through personalized outreach, consultative conversations,
objection handling, structured follow-ups, and guided onboarding.
• Conducted knowledge-transfer sessions for newly onboarded interviewers, improving platform understanding, interview readiness,
and the overall onboarding experience.
• Coordinated with sourcing, onboarding, and operations teams across qualification, job-description confirmation, scheduling,
documentation, and platform activation.
• Maintained accurate pipeline records, communication histories, and onboarding documentation while meeting quality standards
and turnaround times.
• Recognized among the top-performing interns for sourcing quality, onboarding efficiency, confirmation accuracy, and stakeholder
communication
Chip Design Engineer iit gandhinagar · Contract Sep 2025 – Feb 2026 5 mos India Implemented a 5-stage RISC-V through Yosys synthesis, SDC development, floorplanning awareness, STA and physical-design
handoff. Closed target-frequency timing through restructuring/retiming; set clock, I/O and false paths; developed clock constraints
and MMMC awareness.
Analog Design Engineer NIT Silchar · Internship Jun 2025 – Jul 2025 1 mos Silchar, AS, India Benchmarked CMOS, GDI and CML PFDs for propagation delay, dead zone and power. Proposed a hybrid CML-dynamic PFD
with ~45% lower dead zone and zero dead zone above 10 GHz; completed PVT/timing characterization and contributed to an
IEEE manuscript.
Research Intern—Semiconductor Device Simulation Synopsys · Internship Mar 2025 – May 2025 2 mos Bengaluru, KA, India ISWDP—IISc Bangalore, Samsung SSIR & Synopsys (Remote)
• Simulated CMOS devices in TCAD; extracted I–V/C–V, threshold voltage and short-channel effects; analyzed process variation
and device behavior. Completed Samsung-Synopsys ISWDP Level-1 with 86%.

Education

Assam university Bachelor of Technogy, Electronics and Communication Engineering, A 2022 – 2026 Activities and Societies: During my B.Tech at Assam University (2022–2026), I maintained an active involvement in technical societies, cultural activities, student leadership, research, and university event organization alongside my academic work. I was a member of the Astronomy Club, Coding Club, Robotics Club, and VLSI Club, where I participated in technical learning, problem-solving, electronics, robotics, semiconductor, and engineering activities. My involvement in these societies helped me develop practical engineering skills while working collaboratively with students from different technical backgrounds. I was also actively involved in cultural and university activities, particularly singing and event management. I served on the event-organizing team and contributed to the planning and execution of major university events, including the Tech Fest, Engineers’ Day, and Auskriti. These responsibilities involved coordination, communication, scheduling, participant management, and supporting the successful execution of events. I served as the Class Representative during my 3rd year, acting as a communication bridge between students, faculty, and university administration. This role strengthened my leadership, coordination, communication, and problem-solving abilities. Academically, I secured the Topper position in both the 1st and 2nd semesters of my B.Tech program. I was also recognized as the Best Engineer of the B.Tech Batch 2022–2026 and received the “Mr. Engineer” award for engineering excellence and technical contribution. I was awarded Best Debater for my abilities in public speaking, argumentation, critical thinking, and effective communication. My major technical work includes analog and mixed-signal IC design, VLSI, RTL-to-GDSII, digital design, semiconductor device simulation, PLL/PFD research, and biomedical circuit design. Key projects include a 5-stage pipelined RISC-V processor, an ultra-low-power ECG analog front-end, a novel CCRSF OTA, technology-scaled OTA research, a hybrid CML-dynamic PFD for high-speed PLLs, a split-CDAC SAR ADC, a binary-weighted DAC with a two-stage CMOS op-amp, and standard-cell and analog layout. My research work includes three IEEE-format manuscripts covering ultra-low-power ECG AFEs, OTA architecture comparison, and high-speed PFD architectures. I also filed a German Utility Model for an ultra-low-power fully differential ECG analog front-end IC. Alongside technical projects, I founded RenewVolt, a DPIIT-recognized cleantech startup, and worked on engineering and business aspects including embedded power electronics, voltage stabilization, sensing, control, IoT monitoring, documentation, and prototype validation. Overall, my university experience has allowed me to combine academic excellence with analog/VLSI research, hardware engineering, leadership, public speaking, entrepreneurship, teamwork, and large-scale event organization. Active member of the Astronomy, Coding, Robotics, and VLSI Clubs at Assam University, with involvement in singing and major university events as an organizer for Tech Fest, Engineers’ Day, and Auskriti. Served as Class Representative in 3rd year. Academic achievements include Topper of the 1st and 2nd semesters, Best Engineer of the 2022–2026 batch, Best Debater, and “Mr. Engineer” award. Also engaged in analog/VLSI research, hardware projects, IEEE manuscripts, patent-oriented innovation, and founded the DPIIT-recognized startup RenewVolt.
Shrimanta Shankar Academy GED, Science, A+ 2019 – 2020
Shrimanta Shankar Academy 10 th, Science, Outstanding 2017 – 2018 Activities and Societies: Served as School Prefect and was recognized as the Best Academia. Achieved a top-5 ranking in the CBSE Matriculation Examination. I was a among top 1% students in Mathematics and Science Olympiads

Licenses & Certifications

One Month Short Term Course – Challenges and Solutions for Power Quality in Modern Power Electronics Driven Power System Dream Institute of Technology Nov 2025 – Present See credential
VLSI for Beginners NIELIT Calicut Oct 2025 – Present See credential
Embedded Electronics for Beginners NIELIT Calicut Sep 2025 – Present See credential
nternship Completion – Remote Sensing and GIS India Space Academy Aug 2025 – Present See credential
MOOC on FPGA Architecture and Programming – 87/100 NIELIT Calicut Aug 2025 – Present See credential
Satcom Fundamentals: Your First Step into Satellite Comms Udemy Aug 2025 – Present See credential
Overview of Remote Sensing Technology – Online Course ISRO Aug 2025 – Present See credential
Internship / Completion Certificate – Analog Circuit Design & related research work NIT Silchar Aug 2025 – Present See credential
Summer Training Program on Remote Sensing ,GIS and sensor development India Space Academy Jun 2025 – Present See credential
VLSI Analog Mixed Signal Using Synopsys Tools VLSIGuru Jun 2025 – Present See credential
5-Day Hybrid Workshop on Emerging Nanoscale Semiconductor Devices and Integration with Machine Learning Verification NIT Silchar May 2025 – Present See credential
Level 1 – India Semiconductor Workforce Development Program (ISWDP) – Certificate of Participation Samsung Semiconductor India Research May 2025 – Present See credential
Level 1 – India Semiconductor Workforce Development Program (ISWDP) – Certificate of Completion Synopsys May 2025 – Present See credential
Python for Beginners NIELIT Calicut Apr 2025 – Present See credential
VLSI Test Workshop IEEE Mar 2025 – Present See credential
Chip Design – A Fundamental Course (40 Hours) C-DAC Mohali Feb 2025 – Present See credential
Introductory Workshop on Digital Design and 3D Printing IIT Guwahati Feb 2025 – Present See credential