Sree K.
PCB Layout Design Engineer with 20+ Years Exp in Cadence Allegro
Chennai,
India
Global rank:
271,226
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149,894
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About
CORE PCB LAYOUT & HARDWARE SKILLS
High-Speed PCB Layout , High-Power PCB Design , High-Density Multi-Layer PCB , Digital/Analog/Mixed-Signal PCB
DDR5/6, LPDDR5x , PCIe Gen7 , USB / USB 3.2 , SATA , SGMII , UFS , DD-QSFP , MIPI , Ethernet
Fine-Pitch BGA , Large BGA , HDI PCB , Via-in-Pad / On-Pad Via , Blind Vias , Buried Vias
Power Plane Segmentation , Current Rating , Power Distribution Network (PDN) , High-Voltage Clearance & Creepage
Gerber Generation , Fabrication Drawings , Assembly Drawings , BOM , DFM , DFA , Manufacturing Release
Part Decal Creation , Schematic Symbol Creation , Schematic-to-Layout , Design Review ,ECO/Change Support
Tools: Cadence Allegro PCB Editor 24.1 , Altium 26.1 , OrCAD Capture CIS , CAM350 , View Mate , Power DC.
Signal Integrity (SI) , EMI/EMC , Differential Pair Routing , Length Matching , Delay Matching , Tight-Tolerance Routing
Complex multi-layer boards up to 46 layers; probe cards up to 52 layers
Technical leadership, mentoring, stakeholder communication and root-cause analysis
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High-Speed PCB Layout , High-Power PCB Design , High-Density Multi-Layer PCB , Digital/Analog/Mixed-Signal PCB
DDR5/6, LPDDR5x , PCIe Gen7 , USB / USB 3.2 , SATA , SGMII , UFS , DD-QSFP , MIPI , Ethernet
Fine-Pitch BGA , Large BGA , HDI PCB , Via-in-Pad / On-Pad Via , Blind Vias , Buried Vias
Power Plane Segmentation , Current Rating , Power Distribution Network (PDN) , High-Voltage Clearance & Creepage
Gerber Generation , Fabrication Drawings , Assembly Drawings , BOM , DFM , DFA , Manufacturing Release
Part Decal Creation , Schematic Symbol Creation , Schematic-to-Layout , Design Review ,ECO/Change Support
Tools: Cadence Allegro PCB Editor 24.1 , Altium 26.1 , OrCAD Capture CIS , CAM350 , View Mate , Power DC.
Signal Integrity (SI) , EMI/EMC , Differential Pair Routing , Length Matching , Delay Matching , Tight-Tolerance Routing
Complex multi-layer boards up to 46 layers; probe cards up to 52 layers
Technical leadership, mentoring, stakeholder communication and root-cause analysis
Experience
- Lead Engineer – PCB Design & Electronics Hardware GE VERNOVA, CHENNAI. · Full-time May 2026 – Present 5 mos Chennai, Tamil Nadu, India
- Technical Manager HCL Technologies Ltd, CHENNAI. · Full-time Mar 2019 – May 2026 7 yrs 2 mos Chennai, Tamil Nadu, India
- Senior PCB Design Engineer Sanmina-SCI Technologies India Pvt Ltd · Full-time Aug 2014 – Mar 2019 4 yrs 7 mos Chennai, Tamil Nadu, India
- Project Lead L&T Infotech Ltd · Full-time Dec 2010 – Aug 2014 3 yrs 8 mos Chennai, Tamil Nadu, India
- Member Technical staff. HCL Technologies Ltd · Full-time Jun 2007 – Dec 2010 3 yrs 6 mos Chennai, Tamil Nadu, India
Education
- Dr MGR Educational and Research Institute, Maduravoyal B.Tech, ELECRICAL AND TELECOMMUNICATION ENGINEERING 2008 – 2012
Verified info
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Joined: October 6, 2026
Last seen: October 6, 2026
Location
Chennai, India