Global rank:
8,527 / 115,402
Skill pts: 5

About

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Experience

  • Director Odziven Technologies Pvt. Ltd. · Full-time Jan 2025 – Present 11 mos Pune, MH, India I had been working as a freelancer and later joined the firm, to drive the company project activities in the electronics domain (Schematics and PCB Design), Microcontroller coding and FPGA designs. I am very excited to open this firm and looking for the design and product solutions end to end with multiple skillsets in hands.
  • Member of Technical Staff AMD Xilinx Technology Private Limited · Full-time Aug 2021 – Dec 2024 3 yrs 4 mos Hyderabad, TS, India Worked on FPGA designs, AI based designs and help in coding the designs and modules. Owned some of the major design flows for Vivado and Vitis tools.
  • Project Lead Capgemini India Private Limited · Full-time May 2013 – Aug 2021 8 yrs 3 mos Pune, MH, India Deliver multiple projects from High-speed PCB design, SI/PI simulation, Power Electronics board for many industries. Worked on micro controller and FPGA design code.
  • Hardware Design Engineer Intel Technologies India Pvt. Ltd · Full-time Oct 2007 – May 2013 5 yrs 7 mos Bengaluru, KA, India Project Title: High-Speed Laptop Reference board design and Post silicon validation board design
    ​The Challenge: The client needed a compact, multi-layer PCB for a network switch with high-speed 10Gbps Ethernet interfaces. The key challenges were to maintain signal integrity, control impedance, and manage heat dissipation in a small form factor.
    ​My Role: I was responsible for the complete PCB design, from schematic capture to final Gerber file generation. I chose an optimized 10-layer stack-up with dedicated ground planes and used meticulous length matching for all differential pairs.
    ​Key Solutions:
    ​Impedance Control: Performed pre-layout simulations to determine precise trace widths and spacing for 50-ohm single-ended and 100-ohm differential impedances.
    ​Thermal Management: Implemented thermal vias under key components and designed a robust PDN to handle high current loads without excessive heat.
    ​SI Analysis: Conducted post-layout SI analysis using hyperlynx to verify signal integrity and eye diagram openings.
    ​The Result: The design passed SI validation and was fully functional on the first prototype run, saving the client significant time and budget on costly re-spins.

Education

  • AMI Shishu Mandir M.Tech, VLSI Design, A+ 2005 – 2007

Stats

Joined: August 31, 2025

Last seen: September 1, 2025

Location

Pune, India