jedg
Global rank:
31,872 / 32,877
Skill pts: 0
C/C++ Programming CAD Design Cadence Allegro Mentor Graphics

About

Core competency is in circuit design, especially CMOS IC design with experience also at the board level. My skills and experience include VLSI design, firmware, embedded software, and application software development in C++.

My design contributions have led to delivery of a myriad of successful products, often selling in the hundred million volume range worldwide. Innovative achievements, such as in analog circuit design, have contributed to the successful implementation of challenging IC products by meeting design specifications not possible to meet with existing state of the art and with high rate of successful first silicon.

Experience

  • CTO/Design Engineer Gain ICs · Full-time Nov 2012 – Present 7 yrs 10 mos Falcon, CO, United States Innovated and designed instantaneous loops, achieving near ideal phase coherence, using ultrafast phase coordination.

    • Achieved fast loop gain with loop stability, aligning two design goals, eliminating previous conflict, US patent 9,(hidden),(hidden)
    o Tracking bandwidth into the gigahertz (GHz) range, 10,000 times faster than existing loops
    o Ultimately low jitter, elimination of jitter peaking and jitter accumulation

    Innovated and designed ideal wireless, simulating entire wireless physical link, something impossible to achieve with existing methods, enabling quantum advances via eliminating down conversion.

    • Achieved ideal wireless using a novel high-speed phase modulation with only two constellations
    o Transmits 144,000x further
    o Break 1 Gb/s barrier at only 2 to 4 GHz carrier frequency
    o 1/100th narrower occupied bandwidth (greater spectral efficiencies)
    o 1,(hidden),(hidden)x reduction in latencies, demodulation time in low nanoseconds
    o Eliminate interference from multipath reflections
    o Sub-meter accuracy in triangulation locating and velocity measurements
    o Secure communication
  • Analog Design Engineer Atmel · Full-time Feb 2007 – Oct 2012 5 yrs 8 mos Colorado Springs, CO, United States Achieved advances in analog circuitry for chips used in printers, hand-held devices, and embedded security applications.

    • Achieved bandgap and LDO to keep device noise well below 10 uVRMS from 100 to 100 kHz
    o 5uA, chopping at 150 kHz, PSRR -80dB at DC and -70dB at 1kHz, 0.3% across -40 oC to 150 oC
    • Innovated DAC achieving ¼ the DNL of R2R of equivalent power and area, US patent 8,(hidden),(hidden)
    • Innovated a high gain-bandwidth Opposing-currents differential amplifier, US patent 7,(hidden),(hidden)
    o Order of magnitude higher gain-bandwidth than optimally sized differential pair
    o Enabled stable (frequency compensated), 3 stage, 100dB operational amplifiers
    • Innovated differential capacitance sensor, used as a humidity sensor with off-die capacitors
    • Innovated a new self-calibrating temperature sensor, US patent 8,(hidden),(hidden)
    o Sensitivity 0.7mV/ oC (ADC Sensitivity 1.19bit/ oC) from 2.5V to 5.5V with no calibration
    o Silicon measured accuracy 1.26 oC over -15 oC to 100 oC range
    • Achieved a low power two stage Power-on Reset (POR) detector
    o POR signals other circuitry when hand-held battery has degenerated too low
  • Analog IC Design Engineer Intel · Full-time Jun 1997 – Feb 2007 9 yrs 8 mos Hillsboro, OR, United States Achieved key advances to analog circuitry, used across multiple sites.

    • Innovated match-current differential amplifier used in a Pentium 4 PLL, US patents 6,(hidden),(hidden); 6,(hidden),(hidden); 6,(hidden),(hidden)

    o Resulted in substantial reduction in jitter over previous PLLs
    o Published and presented at Intel Design and Test Technology Conference (DTTC) 2000, “Matched Current Differential Amplifiers”
    o Received “Outstanding Presentation” award at DTTC 2000 Design Conference
    o Presented at IEEE ISSCC (Solid-state Conference) 2003, “High frequency system with duty cycle buffer”
    o Consulted cross-sites in their implementation of matched-current differential amplifiers
    • Innovated DR DLL design for tighter windowing in 4 Giga Transfers Second high speed serial link
    o Consulted cross-sites in their implementation of DR DLL, US patent 7,(hidden),(hidden)
    o Paper and presentation given at DTTC 2006 Design Conference
    • Innovated and consulted cross-sites on using large-signal active resistors as terminating resistor, US patents 6,(hidden),(hidden); 6,(hidden),(hidden)
    o Published and presented at IEEE 42nd Midwest Symposium on Circuits and Systems, “Large-signal Active Resistor Output Driver”
    • Achieved and consulted cross-sites on implementing a low DNL 0 oC to 130 oC temperature sensor, US patent 7,(hidden),(hidden)
    • Designed Input/Output cells for Peripheral Component Interconnect (PCI), Accelerated Graphics Port (AGP) 1x to 4x, and memory buses
    o Eliminated Inter Symbol Interference, Common Mode, Electromagnetic Interference and alleviating other high speed effects

Education

  • University of Colorado at Colorado Springs BSEE, CMOS Integrated Circuit Design 1989 – 1993
  • Utah State University BSCS, Computer Science 1982 – 1986

Other experience

  • Software Development Specialist – Consulting / Freelance Developed features for applications used in Microsoft products.

Licenses & Certifications

  • Outstanding Presentation Award Design Technology and Test Conference, Intel May 2000 – Present See credential
Stats

Languages

Spanish Professional working proficiency

Location

Colorado Springs, CO, United States