Sibo P.
Early-career hardware engineer specializing in PCB design, schematic capture, and embedded system de
Tokyo,
Japan
Global rank:
14,426
/
128,609
Skill pts: 5
CAD Design
Cadence Allegro
Cadence Allegro PCB Designer
Cadence OrCAD
RF (Radio-Frequency) Engineering
About
Early-career hardware engineer with a focus on PCB design, schematic capture, and embedded hardware development. Proficient in Cadence Allegro for multi-layer PCB layout, signal routing, and design rule implementation.
Completed projects include socket design for automotive-grade chips, full schematic and PCB development for MCU-based systems, and interface validation for SPI/UART communication. Experienced in component selection, power integrity considerations, and producing manufacturing-ready outputs (Gerber, BOM, documentation).
Strong attention to detail, fast response to client requirements, and ability to deliver clear, production-oriented designs. Bachelor's degree in electronics-related field.
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Completed projects include socket design for automotive-grade chips, full schematic and PCB development for MCU-based systems, and interface validation for SPI/UART communication. Experienced in component selection, power integrity considerations, and producing manufacturing-ready outputs (Gerber, BOM, documentation).
Strong attention to detail, fast response to client requirements, and ability to deliver clear, production-oriented designs. Bachelor's degree in electronics-related field.
Experience
-
Electronic Engineer
Tianma microelectronics · Full-time
Jun 2025 –
Present
10 mos
Shanghai, Shanghai, China
Experience in developing automotive display circuitry, covering schematic design, PCB layout, and system integration. Designed power supply architecture, signal interfaces, and control circuits for in-vehicle display modules, ensuring stable operation under automotive conditions.
Worked on key aspects such as voltage regulation, EMI/EMC considerations, and interface routing for display communication signals. Completed multi-layer PCB layout using Cadence Allegro, with attention to signal integrity, grounding strategy, and manufacturability.
Participated in debugging and validation, including interface testing and basic functional verification, improving overall system reliability. Familiar with automotive design constraints and standard hardware development workflow.
Education
- University of electronic science and technology of china Scholarship Program, Electronic Information Engineering, GPA 3.4 2021 – 2025 Activities and Societies: null
Stats
0 followers, 0 following
Joined: April 8, 2026
Last seen: April 8, 2026
Location
Tokyo, Japan