Remote
Work location
Lead PCB Designer Needed: 6-Layer HDI/Mixed-Signal Industrial Wearable (Strict IPC Class 3 Ended
About the job
Project Overview:
We are finalizing the SHIELD Core V1.2 — a compact (50×40×10 mm) industrial/tactical wearable device. We have a validated engineering architecture, an exploded 3D CAD model, and a finalized component list. We are looking for a senior-level PCB designer who treats signal integrity and thermal management as a religion.
Technical Constraints (Non-negotiable):
Architecture: 6-Layer HDI (High-Density Interconnect).
Fabrication Standard: IPC Class 3.
Specific Challenges:
Analog Isolation: Dedicated ground stitching for MAX30102 PPG sensor.
EMI/Thermal: Massive thermal via arrays under STM32U575 and BQ25185 (PMIC).
RF Integrity: 2.4 GHz ceramic chip antenna integration with a full 6-layer keep-out zone.
Manufacturing: Via-in-Pad (Type VII) for eMMC and BGA/CSP components (must be filled and capped).
What I Expect From You:
DFM Mastery: You don't just "draw traces," you design for automated SMT lines. You understand solder mask defined (SMD) pads for BGA/CSP.
Portfolio: Please provide at least two examples of your previous 6-layer+ HDI work. If you haven't worked with IPC Class 3 or filled vias, please do not apply.
Communication: I need a partner who flags potential issues before the gerbers are sent to the CM, not after.
Project Deliverables:
KiCad project files.
Finalized Gerber set (RS-274X/Excellon) verified against CM’s capability report.
Pick & Place (Centroid) file validation.
BOM review against current supply chain availability.
Why this... read more
We are finalizing the SHIELD Core V1.2 — a compact (50×40×10 mm) industrial/tactical wearable device. We have a validated engineering architecture, an exploded 3D CAD model, and a finalized component list. We are looking for a senior-level PCB designer who treats signal integrity and thermal management as a religion.
Technical Constraints (Non-negotiable):
Architecture: 6-Layer HDI (High-Density Interconnect).
Fabrication Standard: IPC Class 3.
Specific Challenges:
Analog Isolation: Dedicated ground stitching for MAX30102 PPG sensor.
EMI/Thermal: Massive thermal via arrays under STM32U575 and BQ25185 (PMIC).
RF Integrity: 2.4 GHz ceramic chip antenna integration with a full 6-layer keep-out zone.
Manufacturing: Via-in-Pad (Type VII) for eMMC and BGA/CSP components (must be filled and capped).
What I Expect From You:
DFM Mastery: You don't just "draw traces," you design for automated SMT lines. You understand solder mask defined (SMD) pads for BGA/CSP.
Portfolio: Please provide at least two examples of your previous 6-layer+ HDI work. If you haven't worked with IPC Class 3 or filled vias, please do not apply.
Communication: I need a partner who flags potential issues before the gerbers are sent to the CM, not after.
Project Deliverables:
KiCad project files.
Finalized Gerber set (RS-274X/Excellon) verified against CM’s capability report.
Pick & Place (Centroid) file validation.
BOM review against current supply chain availability.
Why this... read more
Project Overview:
We are finalizing the SHIELD Core V1.2 — a compact (50×40×10 mm) industrial/tactical wearable device. We have a validated engineering architecture, an exploded 3D CAD model, and a finalized component list. We are looking for a senior-level PCB designer who treats signal integrity and thermal management as a religion.
Technical Constraints (Non-negotiable):
Architecture: 6-Layer HDI (High-Density Interconnect).
Fabrication Standard: IPC Class 3.
Specific Challenges:
Analog Isolation: Dedicated ground stitching for MAX30102 PPG sensor.
EMI/Thermal: Massive thermal via arrays under STM32U575 and BQ25185 (PMIC).
RF Integrity: 2.4 GHz ceramic chip antenna integration with a full 6-layer keep-out zone.
Manufacturing: Via-in-Pad (Type VII) for eMMC and BGA/CSP components (must be filled and capped).
What I Expect From You:
DFM Mastery: You don't just "draw traces," you design for automated SMT lines. You understand solder mask defined (SMD) pads for BGA/CSP.
Portfolio: Please provide at least two examples of your previous 6-layer+ HDI work. If you haven't worked with IPC Class 3 or filled vias, please do not apply.
Communication: I need a partner who flags potential issues before the gerbers are sent to the CM, not after.
Project Deliverables:
KiCad project files.
Finalized Gerber set (RS-274X/Excellon) verified against CM’s capability report.
Pick & Place (Centroid) file validation.
BOM review against current supply chain availability.
Why this project?
This is a clean-sheet design with zero legacy baggage. You are working with a solid, validated engineering document package. If you are tired of "consumer-grade" projects and want to build industrial-grade hardware that survives the real world, let’s talk.
To prove you’ve read this, start your proposal with your favorite thermal management trick for compact sealed enclosures. read less
We are finalizing the SHIELD Core V1.2 — a compact (50×40×10 mm) industrial/tactical wearable device. We have a validated engineering architecture, an exploded 3D CAD model, and a finalized component list. We are looking for a senior-level PCB designer who treats signal integrity and thermal management as a religion.
Technical Constraints (Non-negotiable):
Architecture: 6-Layer HDI (High-Density Interconnect).
Fabrication Standard: IPC Class 3.
Specific Challenges:
Analog Isolation: Dedicated ground stitching for MAX30102 PPG sensor.
EMI/Thermal: Massive thermal via arrays under STM32U575 and BQ25185 (PMIC).
RF Integrity: 2.4 GHz ceramic chip antenna integration with a full 6-layer keep-out zone.
Manufacturing: Via-in-Pad (Type VII) for eMMC and BGA/CSP components (must be filled and capped).
What I Expect From You:
DFM Mastery: You don't just "draw traces," you design for automated SMT lines. You understand solder mask defined (SMD) pads for BGA/CSP.
Portfolio: Please provide at least two examples of your previous 6-layer+ HDI work. If you haven't worked with IPC Class 3 or filled vias, please do not apply.
Communication: I need a partner who flags potential issues before the gerbers are sent to the CM, not after.
Project Deliverables:
KiCad project files.
Finalized Gerber set (RS-274X/Excellon) verified against CM’s capability report.
Pick & Place (Centroid) file validation.
BOM review against current supply chain availability.
Why this project?
This is a clean-sheet design with zero legacy baggage. You are working with a solid, validated engineering document package. If you are tired of "consumer-grade" projects and want to build industrial-grade hardware that survives the real world, let’s talk.
To prove you’ve read this, start your proposal with your favorite thermal management trick for compact sealed enclosures. read less
Project Overview:
We are finalizing the SHIELD Core V1.2 — a compact (50×40×10 mm) industrial/tactical wearable device. We have a validated engineering architecture, an exploded 3D CAD model, and a finalized component list. We are looking for a senior-level PCB designer who treats signal integrity and thermal management as a religion.
Technical Constraints (Non-negotiable):
Architecture: 6-Laye... read more
We are finalizing the SHIELD Core V1.2 — a compact (50×40×10 mm) industrial/tactical wearable device. We have a validated engineering architecture, an exploded 3D CAD model, and a finalized component list. We are looking for a senior-level PCB designer who treats signal integrity and thermal management as a religion.
Technical Constraints (Non-negotiable):
Architecture: 6-Laye... read more
Project Overview:
We are finalizing the SHIELD Core V1.2 — a compact (50×40×10 mm) industrial/tactical wearable device. We have a validated engineering architecture, an exploded 3D CAD model, and a finalized component list. We are looking for a senior-level PCB designer who treats signal integrity and thermal management as a religion.
Technical Constraints (Non-negotiable):
Architecture: 6-Layer HDI (High-Density Interconnect).
Fabrication Standard: IPC Class 3.
Specific Challenges:
Analog Isolation: Dedicated ground stitching for MAX30102 PPG sensor.
EMI/Thermal: Massive thermal via arrays under STM32U575 and BQ25185 (PMIC).
RF Integrity: 2.4 GHz ceramic chip antenna integration with a full 6-layer keep-out zone.
Manufacturing: Via-in-Pad (Type VII) for eMMC and BGA/CSP components (must be filled and capped).
What I Expect From You:
DFM Mastery: You don't just "draw traces," you design for automated SMT lines. You understand solder mask defined (SMD) pads for BGA/CSP.
Portfolio: Please provide at least two examples of your previous 6-layer+ HDI work. If you haven't worked with IPC Class 3 or filled vias, please do not apply.
Communication: I need a partner who flags potential issues before the gerbers are sent to the CM, not after.
Project Deliverables:
KiCad project files.
Finalized Gerber set (RS-274X/Excellon) verified against CM’s capability report.
Pick & Place (Centroid) file validation.
BOM review against current supply chain availability.
Why this project?
This is a clean-sheet design with zero legacy baggage. You are working with a solid, validated engineering document package. If you are tired of "consumer-grade" projects and want to build industrial-grade hardware that survives the real world, let’s talk.
To prove you’ve read this, start your proposal with your favorite thermal management trick for compact sealed enclosures. read less
We are finalizing the SHIELD Core V1.2 — a compact (50×40×10 mm) industrial/tactical wearable device. We have a validated engineering architecture, an exploded 3D CAD model, and a finalized component list. We are looking for a senior-level PCB designer who treats signal integrity and thermal management as a religion.
Technical Constraints (Non-negotiable):
Architecture: 6-Layer HDI (High-Density Interconnect).
Fabrication Standard: IPC Class 3.
Specific Challenges:
Analog Isolation: Dedicated ground stitching for MAX30102 PPG sensor.
EMI/Thermal: Massive thermal via arrays under STM32U575 and BQ25185 (PMIC).
RF Integrity: 2.4 GHz ceramic chip antenna integration with a full 6-layer keep-out zone.
Manufacturing: Via-in-Pad (Type VII) for eMMC and BGA/CSP components (must be filled and capped).
What I Expect From You:
DFM Mastery: You don't just "draw traces," you design for automated SMT lines. You understand solder mask defined (SMD) pads for BGA/CSP.
Portfolio: Please provide at least two examples of your previous 6-layer+ HDI work. If you haven't worked with IPC Class 3 or filled vias, please do not apply.
Communication: I need a partner who flags potential issues before the gerbers are sent to the CM, not after.
Project Deliverables:
KiCad project files.
Finalized Gerber set (RS-274X/Excellon) verified against CM’s capability report.
Pick & Place (Centroid) file validation.
BOM review against current supply chain availability.
Why this project?
This is a clean-sheet design with zero legacy baggage. You are working with a solid, validated engineering document package. If you are tired of "consumer-grade" projects and want to build industrial-grade hardware that survives the real world, let’s talk.
To prove you’ve read this, start your proposal with your favorite thermal management trick for compact sealed enclosures. read less
Things to know
Intermediate
Skill Level
$300
Fixed-rate (USD)
Part-time
Job type
Under 1-month
Job duration
Areas of expertise
Altium Designer
BOM (Bill of Materials)
EMI/EMC PCB Design
Embedded Systems Design
Embedded Systems Engineering
+2 more
Job categories
PCB Design Services
Electronic Devices
Wearables Design
About the client
Payment ready
Ukraine (10:22 pm)
Posted
Active
Job activity
17 Applicants
0 interviews in progress
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